Reference Flow 6.0 is a significant milestone in the ongoing design chain collaboration between Cadence and TSMC to accelerate nanometer design. Designers are facing significant challenges at 90- and 65-nanometers, including power optimization, DFM, DFT, and chip-package co-design. We're pleased to collaborate with TSMC in Reference Flow 6.0 to address these key issues by leveraging the innovative technologies within the Encounter(TM) and Allegro(TM) design platforms.
Quotes about nanometer (2 Quotes)
As semiconductor manufacturing moves into the sub-100 nanometer range, managing the complex interactions among hundreds of different tools with thousands of different parameters requires comprehensive software systems developed specifically for semiconductor manufacturing.